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XC9536XV High-performance CPLD
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DS053 (v2.2) August 27, 2001
Advance Product Specification
Features
* * 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT IITM switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 3.3V-core XC9536XL device in the 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form.
60 50 200 MHz Typical ICC (mA) 40
nce r ma e rf o er Pow Low
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30 20
H
P ig h
120 MHz
Description
The XC9536XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays of 3.5 ns. See Figure 2 for architecture overview.
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100 150 Clock Frequency (MHz)
200
DS053_01_012501
Figure 1: Typical ICC vs. Frequency for XC9536XV
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS053 (v2.2) August 27, 2001 Advance Product Specification
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XC9536XV High-performance CPLD
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3 JTAG Port 1
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2
DS053_02_041200
Figure 2: XC9536XV Architecture Function block outputs (indicated by the bold line) drive the I/O Blocks directly.
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DS053 (v2.2) August 27, 2001 Advance Product Specification
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XC9536XV High-performance CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Supply voltage for output drivers Input voltage relative to GND(1) Value -0.5 to 2.7 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 3.6 -65 to +150 +260 +150 Units V V V V
oC oC oC
Voltage applied to 3-state output(1) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol VCCINT Parameter Supply voltage for internal logic and input buffers Commercial TA = 0oC to +70oC Industrial TA = -40oC to +85oC Min 2.37 2.37 3.13 2.37 1.71 0 1.7 0 Max 2.62 2.62 3.46 2.62 1.89 0.8 3.6 VCCIO V V V V V V Units V
VCCIO
Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Supply voltage for output drivers for 1.8V operation
VIL VIH VO
Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol TDR NPE VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter Min 20 10,000 2,000 Max Units Years Cycles Volts
DS053 (v2.2) August 27, 2001 Advance Product Specification
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DC Characteristics (Over Recommended Operating Conditions)
Symbol VOH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs VOL Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs IIL Input leakage low current Test Conditions IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.0 90% VCCIO Max 0.4 0.4 0.4 10 Units V V V V V V A
IIH
Input leakage high current
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A
CIN ICC
I/O capacitance Operating Supply Current (low power mode, active)
7
10
pF mA
AC Characteristics
XC9536XV-3 Symbol TPD TSU TH TCO Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Min 2.5 0 0.7 1.8 1.8 4.5 Max 3.5 2.5 277.8 4.3 2.8 2.8 4.9 4.9 7.0 7.5 XC9536XV-4 Min 2.8 0 0.8 2.0 2.0 5.0 Max 4.0 2.8 250.0 4.8 3.2 3.2 5.6 5.6 7.9 8.5 XC9536XV-5 Min 3.5 0 1.0 2.5 2.2 5.0 Max 5.0 3.5 222.2 6.0 4.0 4.0 7.0 7.0 10.0 10.7 XC9536XV-7 Min 4.8 0 1.6 3.2 4.0 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns
fSYSTEM Multiple FB internal operating frequency TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TPLH I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low)
Advance Information
Notes: 1. Please contact Xilinx for up-to-date information on advance specifications.
Preliminary Information
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DS053 (v2.2) August 27, 2001 Advance Product Specification
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XC9536XV High-performance CPLD
VTEST R1 Device Output R2 CL
Output Type
VCCIO 3.3V 2.5V 1.8V
VTEST 3.3V 2.5V 1.8V
R1 320 250 10K
R2 360 660 14K
CL 35 pF 35 pF 35 pF
DS051_03_0601000
Figure 3: AC Load Circuit
Internal Timing Parameters
XC9536XV-3 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay 1.4 1.1 1.4 1.1 3.5 0.5 5.5 1.5 0.5 0.2 1.4 0.8 1.4 2.8 1.5 0 1.2 0.5 3.5 0.1 0.2 4.1 1.6 1.2 1.6 1.2 4.0 0.6 5.6 1.6 0.6 0.2 1.6 1.0 1.6 3.2 1.6 0 1.4 0.6 4.0 0.2 0.2 4.7 2.0 1.5 2.0 1.5 5.0 0.7 5.7 1.6 0.7 0.3 2.0 1.2 2.0 4.0 2.1 0 1.7 0.7 5.0 0.2 0.2 5.9 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 0.8 0.3 2.3 1.5 3.1 5.0 2.5 0 2.4 1.4 7.2 1.3 0.5 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max XC9536XV-4 Min Max XC9536XV-5 Min Max XC9536XV-7 Min Max Units
Product Term Control Delays
Internal Register and Combinatorial Delays
TLOGILP Internal low power logic delay Feedback Delays TF TPTA TPTA2 TSLEW FastCONNECT IITM feedback delay Incremental product term allocator delay Adjacent macrocell p-term allocator delay Slew-rate limited delay Time Adders
3.0 3.0 Advance Information
3.0 4.0 Preliminary Information
Notes: 1. Please contact Xilinx for up-to-date information on advance specifications.
DS053 (v2.2) August 27, 2001 Advance Product Specification
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XC9536XV I/O Pins
Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 2 3 5(1) 4 6(1) 8 7(1) 9 11 12 13 14 18 19 20 22 24 VQ44
CS48 D6 C7 B7(1) C6 B6(1) A6 A7(1) C5 B5 A4 B4 A3 B2 B1 C2 C3 D2 D3
BScan Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54
Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
PC44 1 44 42(1) 43 40(1) 39(1) 38 37 36 35 34 33 29 28 27 26 25 -
VQ44
CS48 D7 E5 E6(1) E7 F6(1) G7(1) G6 F5 G5 F4 G4 E3 F2 G1 F1 E2 E1 E4
BScan Order 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
40 41 43(1) 42 44(1) 2 1(1) 3 5 6 7 8 12 13 14 16 18 -
39 38 36(1) 37 34(1) 33(1) 32 31 30 29 28 27 23 22 21 20 19 -
Notes: 1. Global control pin.
XC9536XV Global, JTAG and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 2.5V VCCIO 1.8vV/2.5V/3.3V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21, 41 32 10, 23, 31 - VQ44 43 44 1 36 34 33 11 9 24 10 15, 35 26 4, 17, 25 CS48 B7 B6 A7 E6 F6 G7 A1 B3 G2 A2 C1, F7 G3 A5, D1, F3 -
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DS053 (v2.2) August 27, 2001 Advance Product Specification
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XC9536XV High-performance CPLD
Ordering Information
Example:
Device Type Speed Grade
XC9536XV -5 PC 44 C
Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -7 -5 -4 -3 7.5 ns pin-to-pin delay 5 ns pin-to-pin delay 4 ns pin-to-pin delay 3.5 ns pin-to-pin delay PC44 VQ44 CS48 Package 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Quad Flat Pack (VQFP) 48-ball Chip Scale Package (CSP) I = Industrial Temperature C = Commercial TA = 0C to +70C TA = -40C to +85C
Component Availability
Pins Type Code XC9536XV -7 -5 -4 -3 44 Plastic PLCC PC44 C, I C (C) (C) 44 Plastic VQFP VQ44 C, I C (C) (C) 48 Plastic CSP CS48 C, I C (C) -
Notes: 1. C = Commercial (TA = 0oC to +70oC); I = Industrial (TA = -40oC to +85oC). 2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information.
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Revision History
Date 02/01/00 01/29/01 05/15/01 08/27/01 Revision No. 1.1 2.0 2.1 2.2 Description Initial Xilinx release. Advance information specification. Added -3 performance specification and VQ44 package. Deleted VQ64 package. Updated ICC vs. Frequency Figure 1. Updated ICC formula, Recommended Operation Conditions, -3, -4, and -5 AC Characteristics and Internal Timing Parameters Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -3 TCGK from 0.3 to 0.8; -5 TAOI from 6.5 to 5.9.
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